Europe’s leading independent nanoelectronics research instituteIMECannounced that it has made significant progress with its 3D-SIC (3D stacked IC) technology. The institute reported a first-time demonstration of 3D integrated circuits obtained by die-to-die stacking and using 5 µm Cu through-silicon vias (TSV). The dies were realized on 200 mm wafers in its reference 0.13 μm CMOS process with an added Cu-TSVs process. For stacking, the top die was thinned down to 25 μm and bonded to the landing die by Cu-Cu thermocompression. IMEC is up-scaling the process for die-to-wafer bonding and is on track for migrating the process to its 300 mm platform. To evaluate the impact of the 3D SIC flow on the characteristics of the stacked layers, both the top and landing wafers contained CMOS circuits. Extensive tests confirmed that the performance of the circuits does not degrade with adding Cu TSVs and stacking. And to test the integrity and performance of the 3D stack, ring oscillators with varying configurations were made, distributed over the two chip layers and connected with the Cu TSVs. Tested after the TSV and stacking process, these circuits demonstrated the chips excellent integrity.
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